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8XC51FX CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS
Commercial/Express
87C51FA/83C51FA/80C51FA/87C51FB/83C51FB/87C51FC/83C51FC See Table 1 for Proliferation Options
Y
High Performance CHMOS EPROM/ROM/CPU 12/24/33 MHz Operation Three 16-Bit Timer/Counters Programmable Counter Array with: - High Speed Output, - Compare/Capture, - Pulse Width Modulator, - Watchdog Timer Capabilities Up/Down Timer/Counter Three Level Program Lock System 8K/16K/32K On-Chip Program Memory 256 Bytes of On-Chip Data RAM Improved Quick Pulse Programming Algorithm Boolean Processor
Y Y Y Y
32 Programmable I/O Lines 7 Interrupt Sources Four Level Interrupt Priority Programmable Serial Channel with: - Framing Error Detection - Automatic Address Recognition TTL Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Controller Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Extended Temperature Range Except for 33 MHz Offering ( b 40 C to a 85 C)
Y Y Y
Y Y Y Y
Y Y Y Y Y
Y
Y Y
Y
MEMORY ORGANIZATION
ROM Device 83C51FA 83C51FB 83C51FC EPROM Version 87C51FA 87C51FB 87C51FC ROMLESS Version 80C51FA 80C51FA 80C51FA ROM/ EPROM Bytes 8K 16K 32K RAM Bytes 256 256 256
These devices can address up to 64 Kbytes of external program/data memory. The Intel 87C51FA/8XC51FB/8XC51FC is a single-chip control oriented microcontroller which is fabricated on Intel's reliable CHMOS III-E technology. The Intel 83C51FA/80C51FA is fabricated on CHMOS III technology. Being a member of the MCS 51 controller family, the 8XC51FA/8XC51FB/8XC51FC uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller products. The 8XC51FA/8XC51FB/8XC51FC is an enhanced version of the 8XC52/8XC54/8XC58. Its added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O and up/down counting capabilities such as motor control. For the remainder of this document, the 8XC51FA, 8XC51FB, 8XC51FC will be referred to as the 8XC51FX, unless information applies to a specific device.
Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT INTEL CORPORATION, 2004 Order Number: 272322-005 July 2004
8XC51FX
Table 1. Proliferation Options Standard 1 -1 -2 80C51FA 83C51FA 87C51FA 83C51FB 87C51FB 83C51FC 87C51FC
NOTES: 1 3.5 -1 3.5 -2 0.5 -24 3.5 -33 3.5 MHz MHz MHz MHz MHz to to to to to 12 16 12 24 33 MHz; 5V MHz; 5V MHz; 5V MHz; 5V MHz; 5V
g20% g20% g20% g20% g10%
-24 X X X X X X X
-33 X X X X X X X
X X X X X X X
X X X X X X X
X X X X X X X
272322 1
Figure 1. 8XC51FX Block Diagram 2
8XC51FX
PROCESS INFORMATION
The 87C51FA/8XC51FB/8XC51FC is manufactured on P629.0, a CHMOS III-E process. Additional process and reliability information is available in the Intel(R) Quality System Handbook: http://developer.intel.com/design/quality/quality.htm
PACKAGES
Part 8XC51FX Package Type 40-Pin Plastic DIP 40-Pin CERDIP 44-Pin PLCC 44-Pin QFP
272322 - 23
PLCC
272322- 2
DIP
* Do not connect Reserved Pins.
272322 - 24
QFP Figure 2. Pin Connections
3
8XC51FX
In addition, Port 1 serves the functions of the following special features of the 8XC51FX: Port Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Alternate Function T2 (External Count Input to Timer/ Counter 2), Clock Out T2EX (Timer/Counter 2 Capture/ Reload Trigger and Direction Control) ECI (External Count Input to the PCA) CEX0 (External I/O for Compare/ Capture Module 0) CEX1 (External I/O Capture Module 1) CEX2 (External I/O Capture Module 2) CEX3 (External I/O Capture Module 3) CEX4 (External I/O Capture Module 4) for Compare/ for Compare/ for Compare/ for Compare/
PIN DESCRIPTIONS
VCC: Supply voltage. VSS: Circuit ground. VSS1: Secondary ground (not on DIP devices or any 83C51FA/80C51FA device). Provided to reduce ground bounce and improve power supply by-passing. NOTE: This pin is not a substitution for the VSS pin. (Connection not necessary for proper operation.) Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1's, and can source and sink several LS TTL inputs. Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program verification. External pullup resistors are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pullups.
Port 1 receives the low-order address bytes during EPROM programming and verifying. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can drive LS TTL inputs. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR). In this application it uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8-bit addresses (MOVX Ri), Port 2 emits the contents of the P2 Special Function Register. Some Port 2 pins receive the high-order address bits during EPROM programming and program verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, on the data sheet) because of the pullups.
4
8XC51FX
Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) When the 8XC51FX is executing code from external Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external Data Memory. EA/V PP: External Access enable. EA must be strapped to VSS in order to enable the device to fetch code from external Program Memory locations 0000H to 0FFFH. Note, however, that if either of the Program Lock bits are programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the programming supply voltage (VPP) during EPROM programming. XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifier.
RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not. An internal pulldown resistor permits a power-on reset with only a capacitor connected to VCC. ALE: Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin (ALE/PROG ) is also the program pulse input during EPROM programming for the 87C51FX. In normal operation ALE is emitted at a constant rate of the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. However, the ALE disable feature will be suspended during a MOVX or MOVC instruction, idle mode, power down mode and ICE mode. The ALE disable feature will be terminated by reset. When the ALE disable feature is suspended or terminated, the ALE pin will no longer be pulled up weakly. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode. Throughout the remainder of this data sheet, ALE will refer to the signal coming out of the ALE/PROG pin, and the pin will be referred to as the ALE/PROG pin. PSEN: Program Store Enable is the read strobe to external Program Memory.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 3. Either a quartz crystal or ceramic resonator may be used. More detailed information concerning the use of the on-chip oscillator is available in Application Note AP-155, Oscillators for Microcontrollers.'' To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 floats, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF.
5
8XC51FX
Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 8XC51FX either hardware reset or external interrupt can cause an exit from Power Down. Reset redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). With an external interrupt, INT0 or INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
272322 3 C1, C2 e 30 pF g10 pF for Crystals For Ceramic Resonators, contact resonator manufacturer.
Figure 3. Oscillator Connections
272322 4
Figure 4. External Clock Drive Configuration
DESIGN CONSIDERATION
Ambient light is known to affect the internal RAM
contents during operation. If the 87C51FX application requires the part to be run under ambient lighting, an opaque label should be placed over the window to exclude light. reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
IDLE MODE
The user's software can invoke the Idle Mode. When the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and the onboard RAM retain their values during Idle, but the processor stops executing instructions. Idle Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can optionally be left running or paused during Idle Mode.
When the idle mode is terminated by a hardware
POWER DOWN MODE
To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Table 2. Status of the External Pins during Idle and Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data
PORT2 Data Address Data Data
PORT3 Data Data Data Data
NOTE: For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), Designing with the 80C51BH.''
6
8XC51FX
ONCE MODE
The ONCE (On-CircuitEmulation'') Mode facilitates testing and debugging of systems using the 8XC51FX without the 8XC51FX having to be removed from the circuit. The ONCE Mode is invoked by: 1) Pull ALE low while the device is in reset and PSEN is high; 2) Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins float, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 8XC51FX is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended temperature range with or without burn-in. With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of 0C to 70 C. With the extended temperature range option, operational characteristics are guaranteed over the range of b 40C to a 85C. The optional burn-in is dynamic for a minimum time of 168 hours at 125 C with VCC =6.9V g 0.25V, following guidelines in MlL-STD-883, Method 1015. For the extended temperature range option, this data sheet specifies the parameters which deviate from their commercial temperature range limits. NOTE: Intel offers Express Temperature specifications for all 8XC51FX speed options except for 33 MHz.
8XC51FX EXPRESS
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS-51 family of microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards.
Table 3. Package Identification Package Type Cerdip PLCC Plastic QFP Cerdip PLCC Plastic QFP Cerdip PLCC Plastic QFP Temperature Range Commercial Commercial Commercial Commercial Extended Extended Extended Extended Extended Extended Extended Extended Burn-In No No No No Yes Yes Yes Yes No No No No
7
8XC51FX
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..- 40C to + 85C Storage Temperature................... - 65C to + 150C
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. * WARNING:Stressing the device beyond the Absolute " Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions'' is not recommended and extended exposure beyond the Operating Conditions'' may affect device reliability.
Power Dissipation............................................... 1.5W (based on PACKAGE heat transfer limitations, not device power consumption)
Voltage on EA/V PP Pin to VSS ............0V to + 13.0V Voltage on Any Other Pin to VSS ... - 0.5V to + 6.5V IOL per I/O Pin.................................................. 15mA
OPERATING CONDITIONS
Symbol TA Description Ambient Temperature Under Bias Commercial Express Supply Voltage 8XC51FX-33 All Others Oscillator Frequency 8XC51FX 8XC51FX-1 8XC51FX-2 8XC51FX-24 8XC51FX-33 Min 0 - 40 4.5 4.0 3.5 3.5 0.5 3.5 3.5 Max + 70 + 85 5.5 6.0 12 16 12 24 33 Units C
VCC
V
fOSC
MHz
DC CHARACTERISTICS
Symbol VIL VIL1 VIH VIH1 VOL Parameter Input Low Voltage Input Low Voltage EA Input High Voltage (Except XTAL1, RST) Input High Voltage (XTAL1, RST)
(Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated.
Min - 0.5 0 0.2 VCC + 0.9 0.7 VCC Typical (Note 4) Max 0.2 VCC -0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3 0.45 1.0 VCC - 0.3 VCC - 0.7 VCC - 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5
- 50
Units V V V V
Test Conditions
Output Low Voltage (Note 5) (Ports 1, 2 and 3) Output Low Voltage (Note 5) (Port 0, ALE/PROG , PSEN) Output High Voltage (Ports 1, 2 and 3 ALE/PROG and PSEN) Output High Voltage (Port 0 in External Bus Mode) 83C51FA/80C51FA (Express)
V
IOL = 100 A IOL = 1.6 mA (Note 1) IOL = 3.5 mA IOL = 200 A IOL = 3.2 mA (Note 1) IOL = 7.0 mA IOH = - 10 A IOH = - 30 A (Note 2) IOH = - 60 A IOH IOH IOH IOH
= = = = - - - -
VOL1
V
VOH
V
VOH1
V
200 A 3.2 mA (Note 2) 7.0 mA 6.0 mA
IIL
Logical 0 Input Current (Ports 1, 2 and 3)
A
VIN = 0.45V
8
8XC51FX
DC CHARACTERISTICS
Symbol ILI ITL
(Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated. (Continued)
Parameter Input leakage Current (Port 0) Logical 1 to 0 Transition Current (Ports 1, 2 and 3) Express Commercial RST Pulldown Resistor Pin Capacitance Power Supply Current: Active Mode At 12 MHz (Figure 5) At 16 MHz At 24 MHz At 33 MHz Idle Mode At 12 MHz (Figure 5) At 16 MHz At 24 MHz At 33 MHz Power Down Mode 40 10 15 20 28 35 5 6 7 7 5 30 38 56 56 7.5 9.5 13.5 15 75 Min Typical (Note 4) Max
g10
Units mA
Test Conditions VIN e VIL or VIH VIN e 2V
b 750 b 650
mA KX pF mA mA mA mA mA mA mA mA mA 1MHz, 25 C (Note 3)
RRST CIO ICC
225
NOTES: 1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic. 2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are stabilizing. 3. See Figures 6 9 for test conditions. Minimum VCC for power down is 2V. 4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V. 5. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 10 mA Maximum IOL per port pin: Maximum IOL per 8-bit port Port 0: 26 mA Ports 1, 2, and 3: 15 mA 71 mA Maximum total IOL for all output pins: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
272322 5
NOTE: ICC max at 33 MHz is at 5V g10% VCC, while ICC max at 24 MHz and below is at 5V g20% VCC.
Figure 5. 8XC51FA/FB/FC I CC vs Frequency
9
8XC51FX
All other pins disconnected TCLCH e TCHCL e 5 ns
272322 6
All other pins disconnected TCLCH e TCHCL e 5 ns
272322 7
Figure 6. I CC Test Condition, Active Mode
Figure 7. I CC Test Condition Idle Mode
All other pins disconnected
272322 8
Figure 8. I CC Test Condition, Power Down Mode. VCC e 2.0V to 6.0V.
272322 19
Figure 9. Clock Signal Waveform for I CC Tests in Active and Idle Modes. TCLCH e TCHCL e 5 ns.
10
8XC51FX
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents)
L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, TAVLL e Time from Address Valid to ALE Low TLLPL e Time from ALE Low to PSEN Low
AC CHARACTERISTICS
(Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 8XC51FX refers to 8XC51FX, 8XC51FX-1 and 8XC51FX-2. Oscillator Symbol Parameter 12 MHz 24 MHz 33 MHz Min 3.5 3.5 0.5 3.5 3.5 127 43 43 21 2TCLCLb 40 TCLCLb 40 TCLCLb 30 TCLCLb 25 TCLCLb 30 TCLCLb 25 4TCLCLb 100 4TCLCLb 75 4TCLCLb 65 TCLCLb 30 TCLCLb 25 3TCLCLb 45 3TCLCLb 105 3TCLCLb 90 3TCLCLb 55 0 ns ns ns ns 11 Variable Max 12 16 12 24 33 Units Min Max Min Max Min Max 1/TCLCL Oscillator Frequency 8XC51FX 8XC51FX-1 8XC51FX-2 8XC51FX-24 8XC51FX-33 TLHLL TAVLL ALE Pulse Width Address Valid to ALE Low 8XC51FX 8XC51FX-24 8XC51FX-33
MHz
ns ns ns ns ns ns ns ns ns ns ns
12
5
TLLAX
Address Hold After ALE Low 8XC51FX/-24 53 8XC51FX-33 ALE Low to Valid Instr In 8XC51FX 8XC51FX-24 8XC51FX-33 ALE Low to PSEN Low 8XC51FX/-24 8XC51FX-33 PSEN Pulse Width PSEN Low to Valid Instr In 8XC51FX 8XC51FX-24 8XC51FX-33 Input Instr Hold after PSEN 0 53 205 145 234
12
5
TLLIV
91
56
TLLPL
12 80
5 46
TPLPH TPLIV
35 0 0
35
TPXIX
8XC51FX
EXTERNAL MEMORY CHARACTERISTICS (Continued) All parameter values apply to all devices unless otherwise indicated
Oscillator Symbol TPXIZ Parameter Input Instr Float After PSEN 8XC51FX 8XC51FX-24 8XC51FX-33 Address to Valid Instr In 8XC51FX/-24 8XC51FX-33 PSEN Low to Address Float 400 400 252 12 MHz 24 MHz 33 MHz Max Min Variable Max TCLCL-25 TCLCL-20 TCLCL-25 5TCLCLb 105 5TCLCLb 80 10 6TCLCLb 100 6TCLCLb 100 5TCLCLb 165 5TCLCLb 95 5TCLCLb 90 0 2TCLCLb 60 2TCLCLb 25 8TCLCLb 150 8TCLCLb 90 9TCLCLb 165 9TCLCLb 90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 TCLCLb 40 TCLCLb 30 TCLCLb 25 TCLCLa 40 TCLCLa 30 TCLCLa 25 ns ns ns ns Units Min Max Min Max Min 59
21
5
TAVIV
312 10 150 150
103 10 82 82
71 10
TPLAZ
TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD Low to Valid Data In 8XC51FX 8XC51FX-24 8XC51FX-33 TRHDX Data Hold After RD TRHDZ Data Float After RD 8XC51FX/24 8XC51FX-33 TLLDV ALE Low to Valid Data In 8XC51FX 8XC51FX-24/33
113 0 0 23
61
0 107
35
517
243
150
TAVDV Address to Valid Data In 8XC51FX 8XC51FX-24/33 TLLWL ALE Low to RD or WR Low TAVWL Address to RD or WR Low 8XC51FX 8XC51FX-24 8XC51FX-33 TQVWX Data Valid to WR Transition 8XC51FX 8XC51FX-24/33 TWHQX Data Hold After WR 8XC51FX 8XC51FX-24 8XC51FX-33 TQVWH Data Valid to WR High 8XC51FX 8XC51FX-24/33 TRLAZ RD Low to Address Float
585 200 300 203 75
285 175 41
180
140 3TCLCLb 50 3TCLCLa 50 4TCLCLb 130 4TCLCLb 90 4TCLCLb 75 TCLCLb 50 TCLCLb 30 TCLCLb 50 TCLCLb 35 TCLCLb 27 7TCLCLb 150 7TCLCLb 70 0
77
46
33
12
0
33
7
3
433 0 123
222 0
142
TWHLH RD or WR High to ALE High 8XC51FX 43 8XC51FX-24 8XC51FX-33
12
71
5
55
12
8XC51FX
EXTERNAL PROGRAM MEMORY READ CYCLE
272322 9
EXTERNAL DATA MEMORY READ CYCLE
272322 10
EXTERNAL DATA MEMORY WRITE CYCLE
272322 11
13
8XC51FX
SERIAL PORT TIMINGSHIFT REGISTER MODE Test Conditions:
Symbol TXLXL Parameter Serial Port Clock Cycle Time Over Operating Conditions; Load Capacitance e 80 pF Oscillator 12 MHz Min 1 Max 24 MHz Min 0.50 33 MHz Max Min 12TCLCL 0.36 Variable Max ms Units Max Min
TQVXH Output Data Setup to Clock Rising Edge TXHQX Output Data Hold After Clock Rising Edge 8XC51FX 8XC51FX-24/33 TXHDX Input Data Hold After Clock Rising Edge TXHDV Clock Rising Edge to Input Data Valid
700
284
167
10TCLCLb 133
ns
50 0
34 0
10 0
2TCLCLb 117 2TCLCLb 50 0
ns ns ns
700
283
167
10TCLCLb 133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
272322 12
14
8XC51FX
EXTERNAL CLOCK DRIVE
Symbol 1/TCLCL Parameter Oscillator Frequency 8XC51FX 8XC51FX-1 8XC51FX-2 8XC51FX-24 8XC51FX-33 High Time 8XC51FX-24/33 Low Time 8XC51FX-24/33 Rise Time 8XC51FX-24 8XC51FX-33 Fall Time 8XC51FX-24 8XC51FX-33 Min 3.5 3.5 0.5 3.5 3.5 20 0.35 TOSC 20 0.35 TOSC Max 12 16 12 24 33 0.65 TOSC 0.65 TOSC 20 10 5 20 10 5 Units MHz MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns
TCHCX TCLCX TCLCH
TCHCL
EXTERNAL CLOCK DRIVE WAVEFORM
272322 13
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
272322 14 AC Inputs during testing are driven at VCCb 0.5V for a Logic 1'' and 0.45V for a Logic 0''. Timing measurements are made at VIH min for a Logic 1'' and VOL max for a Logic 0''.
272322 15 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/V OL level occurs. IOL/I OH e g20 mA.
15
8XC51FX
Normally EA/V PP is held at logic high until just before ALE/PROG is to be pulsed. Then EA/V PP is raised to VPP, ALE/PROG is pulsed low, and then EA/V PP is returned to a valid high voltage. The voltage on the EA/V PP pin must be at the valid EA/V PP high level before a verify is attempted. Waveforms and detailed timing specifications are shown in later sections of this data sheet. NOTE:
PROGRAMMING THE EPROM/OTP
To be programmed, the part must be running with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal EPROM locations.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2.0 - P2.4 of Port 2, while the code byte to be programmed into that location is applied to Port 0. The other Port 2 and 3 pins, RST PSEN, and EA/V PP should be held at the Program'' levels indicated in Table 4. ALE/PROG is pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 10.
EA/V PP pin must not be allowed to go above the
maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The VPP source should be well regulated and free of glitches.
Table 4. EPROM Programming Modes Mode Program Code Data Verify Code Data Program Encryption Array Address 0 3FH Program Lock Bits Bit 1 Bit 2 Bit 3 Read Signature Byte RST H H H H H H H PSEN L L L L L L L H H ALE/ PROG EA/ VPP 12.75V H 12.75V 12.75V 12.75V 12.75V H P2.6 L L L H H H L P2.7 H L H H H L L P3.3 H L H H H H L P3.6 H H L H L H L P3.7 H H H H L L L
See Table 4 for proper input on these pins
272322 20
Figure 10. Programming the EPROM
16
8XC51FX
Repeat 1 through 5 changing the address and data for the entire array or until the end of the object file is reached.
PROGRAMMING ALGORITHM
Refer to Table 4 and Figures 10 and 11 for address, data, and control signals set up. To program the 87C51FX the following sequence must be exercised. 1. Input the valid address on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/V PP from VCC to 12.75V g0.25V. 5. Pulse, ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and the lock bits.
PROGRAM VERIFY
Program verify may be done after each byte or block of bytes is programmed. In either case a complete verify of the programmed array will ensure reliable programming of the 87C51FX. The lock bits cannot be directly verified. Verification of the lock bits is done by observing that their features are enabled.
272322 21
Figure 11. Programming Signals Waveforms
ROM and EPROM Lock System
The 87C51FX program lock system, when programmed, protects the onboard program against software piracy. The 83C51FX has a one-level program lock system and a 64-byte encryption table. See line 2 of Table 5. If program protection is desired, the user submits the encryption table with their code, and both the
lock-bit and encryption array are programmed by the factory. The encryption array is not available without the lock bit. For the lock bit to be programmed, the user must submit an encryption table. The 83C51FA does not have protection features. The 87C51FX has a 3-level program lock system and a 64-byte encryption array. Since this is an EPROM device, all locations are user-programmable. See Table 5.
Table 5. Program Lock Bits and the Features Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U No Program Lock features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, also external execution is disabled. 17 ProtectIon Type
3 4
P P
P P
U P
Any other combination of the lock bits is not defined.
8XC51FX
bytes in locations 30H and 31H. To read these bytes follow the procedure for EPROM verify, but activate the control lines provided in Table 4 for Read Signature Byte. Location 30H 31H 60H Device All All 83C51FA 87C51FA 83C51FB 87C51FB 83C51FC 87C51FC Contents 89H 58H 7AH/FAH FAH 7BH/FBH FBH 7CH/FCH FCH
Encryption Array
Within the EPROM array are 64 bytes of Encryption Array that are initially unprogrammed (all 1's). Every time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed (XNOR) with the code byte, creating an Encryption Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in its original, unmodified form. For programming the Encryption Array, refer to Table 4 (Programming the EPROM). When using the encryption array, one important factor needs to be considered. If a code byte has the value 0FFH, verifying the byte will produce the encryption byte value. lf a large block (l 64 bytes) of code is left unprogrammed, a verification routine will display the contents of the encryption array. For this reason all unused code bytes should be programmed with some value other than 0FFH, and not all of them the same value. This will ensure maximum program protection.
Erasure Characteristics (Windowed Packages Only)
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm. Exposing the EPROM to an ultraviolet lamp of 12,000 mW/cm rating for 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves all the EPROM Cells in a 1's state.
Program Lock Bits
The 87C51FX has 3 programmable lock bits that when programmed according to Table 5 will provide different levels of protection for the on-chip code and data. Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to full functionality.
Reading the Signature Bytes
The 87C51FX has 3 signature bytes in locations 30H, 31H, and 60H. The 83C51FA has 2 signature
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8XC51FX
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA e 21 C to 27 C; VCC e 5V g20%; VSS e 0V) Symbol VPP IPP 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ TGHGL Parameter Programming Supply Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG P2.7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float after ENABLE PROG High to PROG Low 0 10 4 48TCLCL 48TCLCL 48TCLCL 48TCLCL 48TCLCL 10 10 90 110 48TCLCL 48TCLCL 48TCLCL ms ms ms ms Min 12.5 Max 13.0 75 6 Units V mA MHz
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
272322 18
NOTE: 5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
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8XC51FX
Thermal Impedance
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and applications. See the Intel Packaging Handbook (Order No. 240800) for a description of Intel's thermal impedance test methodology.
Device All 80C51FA, 83C51FA, 8XC51FC 87C51FA, 8XC51FB All FA FB FC
i JA
i JC
45C/W 16C/W 36C/W 13C/W 45C/W 46C/W 97C/W 96C/W 87C/W 15C/W 16C/W 24C/W 24C/W 18C/W
DATA SHEET REVISION HISTORY
Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices.
The following differences exist between this datasheet (272322-005) and the previous version (272322-004): 1. Product prefix variables are now indicated with an x. The following differences exist between this datasheet (272322-003) and the previous version (272322-002): 1. Removed 8XC51FX-3 and 8XC51FX-20, replaced with 8XC51FX-24. 2. Included 8XC51FX-24 and 8XC51FX-33 devices. 3. 80C51FA and 83C51FA now have the same features as 87C51FA, 8XC51FB and 8XC51FC; same DC spec used for all devices. The following differences exist between the -002'' and -001'' version of 8XC51FX datasheet: 1. Removed 8XC51FX-L from datasheet. 2. Include VOH1 for 83C51FA (Express)/80C51FA (Express). This 8XC51FX datasheet (272322-001) replaces the following datasheets: 87C51FA/83C51FA/80C51FA 83C51FA/80C51FA EXPRESS 87C51FA EXPRESS 87C51FA-20/-3 87C51FB/83C51FB 87C51FB-20/-3 83C51FB-20/-3 87C51FB/83C51FB EXPRESS 87C51FC/83C51FC 87C51FC/83C51FC EXPRESS 87C51FC-20/-3 83C51FC-20/-3 270258-007 270620-001 270619-001 272081-002 270563-005 272080-002 270767-002 270789-004 270903-001 272028-002
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